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1
Flip-Flop Design in Nanometer CMOS: From High Speed to Low Energy
Springer International Publishing
Massimo Alioto
,
Elio Consoli
,
Gaetano Palumbo (auth.)
clock
delay
ffs
variations
slope
topologies
input
transistors
circuits
gate
flip
impact
pulsed
leakage
effort
sizing
circuit
speed
output
tgpl
fo4
capacitance
efficient
tgff
equal
path
transistor
flop
sensitivity
paths
optimization
logical
values
normalized
slave
voltage
analysis
gates
shown
layout
vdd
capacitances
sdq
stages
optimum
cmos
current
parameters
considering
edge
Godina:
2015
Jezik:
english
Fajl:
PDF, 10.40 MB
Vaši tagovi:
0
/
0
english, 2015
2
Lifetime Reliability-aware Design of Integrated Circuits
Springer
Mohsen Raji
,
Behnam Ghavami
reliability
lifetime
gate
delay
circuit
timing
aging
circuits
ffs
optimization
effects
gates
degradation
technique
nbti
proposed
modified
transistors
bti
transistor
sizing
criticality
vth
improvement
analysis
variations
algorithm
δv
clock
original
node
probability
doi.org
statistical
constraint
voltage
metric
considering
integrated
method
joint
threshold
impacts
parameters
stress
induced
output
presented
random
tyr
Godina:
2023
Jezik:
english
Fajl:
PDF, 3.84 MB
Vaši tagovi:
0
/
0
english, 2023
3
Lifetime Reliability-aware Design of Integrated Circuits
Springer
Mohsen Raji
,
Behnam Ghavami
reliability
lifetime
gate
delay
circuit
timing
aging
circuits
ffs
optimization
effects
gates
degradation
technique
nbti
proposed
modified
transistors
bti
transistor
sizing
criticality
vth
improvement
analysis
variations
algorithm
δv
clock
original
node
probability
doi.org
statistical
constraint
voltage
metric
considering
integrated
method
joint
threshold
impacts
parameters
stress
induced
output
presented
random
tyr
Godina:
2022
Jezik:
english
Fajl:
PDF, 3.76 MB
Vaši tagovi:
0
/
5.0
english, 2022
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